An example of the A/D (Analog to Digital) converting method used in recent imaging devices is a method called column A/D which installs an A/D converter for each pixel column of an image sensor. An example of A/D conversion used in column A/D is an integrating type A/D conversion. Japanese Patent Laid-Open No. 2005-348325 discloses in particular a multi-step scheme which performs A/D conversion in two or more steps divisionally for higher and lower bits.
Japanese Patent Laid-Open No. 2005-348325 discloses an imaging device including sensing elements arranged in a two-dimensional array, and A/D converters provided in a one-to-one-correspondence with the columns of sensing elements. In this imaging device, each A/D converter holds, in a storage unit, an electrical signal corresponding to the analog signals of sensing elements as an initial value. The storage unit is charged or discharged by a first fixed signal input after that. Time is discretely measured from the start of charge or discharge until the electrical signal in the storage unit reaches a reference signal. The storage unit is discharged or charged by a second fixed signal input after that. The time until the electrical signal in the storage unit which has exceeded the reference signal, after the measurement reaches the reference signal, is discretely measured as a digital value. More specifically, the output from an integrator is set as a pixel signal voltage, and integration then starts as a negative slope. At a certain time, the output of the integrator falls below the reference voltage, and A/D conversion of N higher bits ends. Integration is temporarily interrupted at the end. However, since switches are controlled in discrete time, the difference between the integrator output and the reference voltage is not 0, and a potential difference (residual signal) exists between them. In the next step, the first potential difference is integrated again, thereby converting M lower bits. At a certain time later, the output of the integrator intersects the reference voltage of the comparator, and A/D conversion of M lower bits ends.
However, in the above-described prior art, if the residual signal that is the difference between the reference voltage and the integrator output after higher conversion contains an offset caused by leakage, delay, or the like, determination may be unable to finish until the end of the lower count period, or conversely, the output from the comparator may be inverted before lower conversion count. In this case, the conversion linearity becomes more poor.